There are numerous interposers and methods for making and using these interposers in the prior art. Interposers are used for different purposes. Generally, interposers provide an interface between two electrical components, such as one or more semiconductor devices and a printed circuit board, or two printed circuit boards. For example, an interposer can be used to interface a semiconductor wafer to a probe card for testing of the dies on the wafer to determine which dies are good. A wafer tester or prober may be advantageously employed to make a plurality of discrete pressure connections to a like plurality of discrete contact elements (e.g. bonding pads) on the dies. In this manner, the semiconductor dies can be tested, for example, to determine whether the dies are non-functional or partially functional (each, “bad” die), prior to singulating the dies from the wafer.
Testing of semiconductor devices is performed on various levels. For example, in very advanced systems, semiconductor devices may be tested for performance operations, while still in wafer form, under various temperature and environmental conditions. This type of testing is commonly referred to as “wafer level test.” Referring to FIG. 1, a test assembly 100 is shown to illustrate a technique for performing wafer-level test and/or wafer level burn-in of semiconductor devices included in a test substrate (application specific integrated circuits (ASIC) 106 and base plate 108, collectively) having active electronic components such as ASICs 106a-106d, mounted to an interconnection substrate or incorporated therein. See commonly assigned U.S. Pat. No. 6,064,213 entitled “Wafer-Level Burn-In and Test”, which is herein incorporated by reference as though set forth in full. Spring contact elements 110 effect interconnections between the ASICs 106a-106d (ASICs 106a-106d generally comprise the ASICs 106) and a plurality of devices-under-test (DUTs), 102a-102d, on a wafer-under-test (WUT) 102. In one embodiment, the assembly is disposed in a vacuum vessel with independent temperature regulation so that the ASICs can be operated at temperatures independent from and in many instances significantly lower than the burn-in temperature of the DUTs. The spring contact elements 110 may be mounted to either the DUTs 102a-102d or the ASICs 106a-106d, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs 106 and the DUTs 102. For the connection 120 to the host controller, a significant reduction in interconnect count and consequent simplification of the interconnection substrate is realized because the ASICs are capable of receiving a plurality of signals for testing the DUTs over relatively few signal lines from a host controller 116 and promulgating these signals over the relatively many interconnections 110 between the ASICs 106 and the DUTs 102. The ASICs 106 can also generate at least a portion of these signals in response to control signals from the host controller 116. Physical alignment techniques are also described in the reference.
During testing, a power supply 118 provides power signals to the ASICs through a base plate 108 connected to an upper portion of a chuck 104a used for holding the test assembly in place with the assistance of guide pins 112. While operational, i.e. under test, force is applied in the z-direction bringing the ASICs 106 in contact with the spring contact element 610 and compressing the latter to a position determined by compression stops 114, which are positioned at either end of the wafer 102. The compression stops function to stop the base plate 108 from moving down in the z-direction thereby determining the extent to which the spring contact elements 110 are compressed and thus avoiding over-compression of the latter.
FIG. 2 illustrates an alternative test assembly 200 including a wafer 202, an interposer 204 and a tester contactor 206. On both surfaces of the interposer, solder balls 210 are formed in order to interconnect wafer 202 to tester contactor 206. The contact pads 208 on wafer 202 come in contact with solder balls 210 on the top surface of interposer 204 when wafer 202 is lowered toward tester contactor 206. Upon further lowering of wafer 202, solder balls 212 on the bottom surface of interposer 204 come in contact with the contact pads 214 of the tester contactor 206, thereby establishing electrical connection between wafer 202 and the tester through tester contactor 206. Typically, a wafer can have in excess of 10,000 contact pads. For instance, a 200 mm wafer may have 20-50 thousand contact pads. To establish reliable connections between such a large number of contact pads between the wafer and the tester is a significant challenge.
In prior art wafer-level testing techniques, the interconnection elements reside on the wafer or the contactor (wiring layer). While this prior art approach provides certain advantages, it also has certain limitations. For example, when the interconnection elements or springs reside on the wafer or contactor, a modular construction approach cannot be implemented for a burn-in system. Similarly, the use of solder balls on the interposer does not permit a modular construction.
It is noted that there are certain existing double-sided interconnection substrates, such as shown in commonly assigned U.S. Pat. No. 5,917,707, entitled “Flexible Contact Structure With An Electrically Conductive Shell” (for example, FIG. 36), and commonly assigned U.S. patent application Ser. No. 08/452,255, entitled Electrical Contact Structures Formed By Configuring A Flexible Wire To Have A Springable Shape And Covercoating The Wire With At Least One Layer Of A Resilient Conductive Material, Methods Of Mounting The Contact Structures To Electronic Components, And Applications For Employing The Contact Structures” (for example, FIG. 39). These prior art substrates, however, do not address completely certain wafer-level testing needs.
A need therefore exists for an improved interposer and a method for making and using the same without the need to connect resilient interconnect elements or other types of interconnect elements onto the DUT and/or the device being packaged.